The present invention relates to semiconductor integrated circuits and the manufacture thereof. The invention is illustrated in an example with regard to an application specific integrated circuit (ASIC) with circuit elements such as power/ground lines, peripheral circuits, and break cells, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in other semiconductor integrated circuits such as custom integrated circuits, standard products including at least microprocessors (MICROs) and memory products (MEMORY), programmable circuits, among others.
The design of power/ground lines and peripheral circuits to meet power supply needs for ASICs is generally known in the art. Various power supply voltage levels can be used with different ASIC types to supply power to each of its circuit elements. A conventional ASIC with a core region and peripheral circuits typically operates under a fixed power supply condition. The conventional ASIC often operates at the fixed power supply condition to function under a certain high/low switching level for the specified technology such as TTL (transistor-transistor-logic), ISL/STL (integrated Schottky logic/Schottky transistor logic), ECL (emitter-coupled logic), IIL (integrated injection logic), among others. In addition, the peripheral circuits such as buffers are often designed at such power supply level for a certain high and low (V.sub.H /V.sub.L) input/output (I/O) signal level to accommodate the switching level technology.
As integrated circuits become denser and operate at higher speeds, it is often desirable to design integrated circuits using a lower power supply voltage level to improve circuit characteristics such as power consumption, switch speed, reliability, and the like. For example, a conventional ASIC typically uses a power supply voltage level of either 5 volts or 3.3 volts to power-up its circuit elements. This means that such ASIC may operate at either a fixed 3.3 volt or 5 volt power supply level, but generally not both. However, it may occur that a user desires certain characteristics of the 5 volt integrated circuit power supply design and the lower 3.3 volt or even a lower power supply voltage design. The conventional ASIC typically cannot operate at a different power supply voltage level which often limits the use of such ASIC to its fixed power supply voltage level.
In addition, the conventional ASIC which relies upon the fixed power supply voltage condition cannot typically adapt certain pins designed for use with a certain set of V.sub.H /V.sub.L signal levels to another set of high and low signal levels. These problems may be illustrated in a conventional ASIC of FIG. 1.
The conventional ASIC 10 of FIG. 1 illustrates a general ASIC configuration using, for example, CMOS technology. The ASIC includes a core region 13, peripheral circuits 15 such as buffers, I/Os, or the like, and bond pads 17. The core region 13 and peripheral circuits 15 are generally represented as part A and part B, respectively. The core region and peripheral circuits are designed to operate at a fixed power supply voltage level such as 3.3 or 5 volts, and are often limited to such fixed power supply voltage level for a particular ASIC type.
For example, the core region power supply voltage which is designed at 3.3 volt cannot easily be changed to an operating condition of 5 volts when the circuit has been designed with a single 3.3 volt power supply and peripheral buffers also designed at 3.3 volt. In particular, the power routing is typically not designed to allow for the core region to be changed from 3.3 volt operation to 5 volt operation without also changing the power supply level of the peripheral buffers. Accordingly, the conventional ASIC has a core region which may not be changed to a different power supply voltage level.
Certain peripheral circuits and/or buffers cannot easily be adapted in the conventional ASIC to a change in high and low voltage signal levels from one set of signal levels to another different set of signal levels without effecting other peripheral circuits. These circuit elements are typically designed to accommodate a single set of voltage signal levels and therefore may not easily be adapted to accommodate the other different set of high and low voltages which correspond to the signal levels. In addition, should the power supply voltage level that is different from the designed level be applied to the peripheral buffers, certain circuit elements often tend to function improperly.
FIG. 2 depicts a portion 20 of the peripheral circuits for the ASIC of FIG. 1 where a supply voltage level different from the designed level is applied to a CMOS inverter. For illustrative purposes only, inverter 21 and inverter 22 are connected to power bus lines 23 and 24 at 3.3 volts and 5 volts, respectively. Each inverter includes an n-type channel field effect (nMOS) Q.sub.B transistor and a p-type channel field effect transistor (pMOS) Q.sub.A, typifying CMOS technology. Inverter 21 includes the 3.3 volt power source at a source/drain of Q.sub.A, an input 25, and an output 26. The output 26 from inverter 21 drives inverter 22 which includes a source/drain of Q.sub.A at 5 volts, an input 26, and an output 27. A problem of direct current (DC) power consumption at inverter 22 occurs when the lower 3.3 volt output 26 of inverter 21 drives inverter 22 which has power at 5 volts. DC power consumption often reduces the switching capability of the pMOS transistor 30 at inverter 22, and may effect the signal voltage at the output 27. Further, the existing power bus configuration of the conventional ASIC does not easily adapt to a different power supply level for each inverter as illustrated.
The problems described herein also exist with other integrated circuits such as custom integrated circuits, standard products including at least microprocessors (MICROs) and memory products, gate arrays, programmable circuits, and the like. Such integrated circuits may employ a technology which includes metal oxide silicon field effect transistor (MOS), complementary metal oxide silicon field effect transistor (CMOS), bipolar complementary metal oxide silicon field effect transistor (BiCMOS), bipolar transistor (bipolar), among ethers.
From the above it is seen that a method and structure is needed for providing variable supply power and/or I/O voltage levels to certain semiconductor integrated circuits elements.